Fully depleted silicon-on-insulator (FDSOI) technology is a planar process technology that relies on two primary features. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon. Then, a thin silicon film implements the transistor channel. Due to the thinness of the silicon, there is no need to dope the channel, therefore making the transistor fully depleted. FDSOI enables significant improvement in transistor electrostatic characteristics versus conventional bulk technology. For example, the buried oxide layer lowers the parasitic capacitance between the source and the drain. Further, when compared with conventional bulk technology, FDSOI also efficiently confines the electrons flowing from the source to the drain, dramatically reducing performance-degrading leakage currents.
Three-dimensional (3D) integrated circuit (IC) devices utilize stacked wafers and/or dies that are vertically interconnected using through-silicon vias (TSVs), so that the wafers or dies perform as a single device. 3D ICs can provide enhanced performance, with reduced power usage (and a smaller footprint) than conventional two-dimensional IC devices.
Capitalizing on both technological advancements is the deployment of FDSOI dies in 3D IC devices. These 3D FDSOI devices include stacked FDSOI dies formed from distinct FDSOI wafers (or, wafer lots). However, because these dies are sourced from different wafers (or wafer lots), these dies commonly have different process performance distributions (e.g., fast, slow, nominal) tailored to the particular devices for which such wafers are formed. This performance “mismatch” can make it difficult to construct a 3D FDSOI device to meet performance requirements while maintaining a desirable yield in the wafers.